Description du sujet de thèse

Development of measurement methods for the assessment of risk-based approach to EMC at IC level

Context and issues

In recent years, the transport sector has undergone major transformations linked to technological developments leading to more electrified and autonomous vehicles. EMC-related issues are becoming even more essential to prevent any risk of malfunction linked to electromagnetic (EM) disturbances, and to guarantee user operating safety. The growing complexity of EM environments, combined with the growing need to ensure the reliability of on-board electronic equipment (e.g. for automotive, aeronautical or space applications), means that it is crucial to assess the risk posed by EM disturbances to the operational integrity of electronic components under realistic operating conditions.

The conventional rule-based approach to EMC validation assumes that compliance with EMC limits, verified by standard test methods, is sufficient to guarantee the absence of any risk of EM failure, even in a worst-case scenario. In the case of integrated circuits (ICs), this approach is based in particular on characterizing IC immunity to RF disturbances (harmonics) as defined by standard IEC 62132 [1]. These tests are generally supplemented by immunity tests to electrostatic discharge and electrical fast transients, during which ICs are subjected to standard waveforms [2] [3]. During all these tests, the ICs are operated under nominal conditions and in controlled environments.

For various reasons, however, it is questionable whether such an approach is able to assess the risk of malfunctions linked to EM disturbances for safety-critical electronic components or systems. Indeed, current EMC test methods do not necessarily anticipate actual operating conditions and their effects on electronic circuits, such as failure or aging. For example, immunity is rarely tested under conditions that could lead to malfunction (e.g. high temperature or short-circuit of a phase of a wave arm). The integrity of fault detection mechanisms is rarely assessed in the presence of electromagnetic disturbances, which can nevertheless degrade operational reliability. Furthermore, the disturbances applied during testing are defined by canonical waveforms that remain far removed from those encountered in real EM environments (e.g. multi-frequency disturbances, transient disturbances of arbitrary shape). Furthermore, EMC test methods do not provide for simultaneous injections on different pins of a component or system.

For several years now, this “rule-based approach” has been called into question by many experts [4]. Recent changes to the European EMC Directive have moved it towards a risk-based approach for EMC [5], whereby the EMC assessment should consider all operating conditions and configurations of the system during its lifetime. However, due to budgetary constraints and time-to-market delays, industry is reluctant to carry out more exhaustive EMC testing. To overcome these problems and develop a risk-based approach to EMC, it is necessary to develop EMC test methods that enable risk assessment. These must be sufficiently representative of operating conditions and environments, while optimizing test costs and times. This requires not only the development of an EM risk analysis method, leading to the proposal of a suitable EMC test line, but also the development of sufficiently rapid EMC measurement methods to assess EM risk.

The European EMC Directive applies to systems, so the question arises as to how to transpose a risk-based approach to IC EMC. This question is far from trivial, since risk assessment depends on the final application and its environment, which are not fully known to the IC designer.




Research subject
The proposed thesis is part of the CEMASURF (Compatibilité ElectroMAgnérique et SÛReté de Fonctionnement d'électronique embarquée) project, proposed in partnership with NXP Semiconductor and Nexio. The aim of this project is to develop test and simulation methods to improve the assessment of risk caused by electromagnetic disturbances in embedded electronic systems, and more specifically in ICs.
The objectives of the PhD thesis are multifold:
 Propose an EM risk analysis method at IC level, in order to define an EMC test line to be applied to ICs.
 Propose rapid EMC test methods for assessing EM risks in complex EM environments (e.g. multitone disturbances, any transient disturbances applied simultaneously with harmonic disturbances, disturbances coupled simultaneously on several pins of a circuit).
 Propose fast EMC test methods to test and evaluate the integrity of fault detection mechanisms embedded within ICs.
 In addition, these EMC test methods should enable the development of model-based approaches to risk prediction.

The thesis work will build on recent work carried out on the risk-based EMC theme, and in particular on the work of the LAAS ESE team on the use of multitone generators to rapidly analyze and classify the nature of IC response to complex EM disturbances [6] [7]. The concepts proposed and developed during this thesis will be tested and validated on two types of applicative case studies from the transport and space sectors: a powertrain demonstrator for an electric vehicle, and a communication bus in a nanosatellite. The work carried out in this thesis will serve as a basis for reflection on the evolutions to be made to circuit EMC test standards.

Contexte de travail

The thesis will be carried out within the LAAS-CNRS laboratory and the Energy and Embedded Systems team. It is part of the CEMASURF (Compatibilité ElectroMAgnérique et SÛReté de Fonctionnement d'électronique embarquée) project, proposed in partnership with NXP Semiconductor, Airbus and Nexio.

Le poste se situe dans un secteur relevant de la protection du potentiel scientifique et technique (PPST), et nécessite donc, conformément à la réglementation, que votre arrivée soit autorisée par l'autorité compétente du MESR.