Description du sujet de thèse

Context: The design of cryogenic silicon circuits has gained much importance in recent years, in particular for applications such as silicon quantum computers that require interface electronics with ultra-low levels of power consumption at temperatures as low as 4 K. The design of these circuits is complicated due to the lack of standard design kits for their simulation at these temperatures. Alternative approaches to avoid costly design and fabrication cycles for the optimization of these circuits are possible, in particular the use of Look-Up-Table (LUT)-based techniques that exploit the characterization of components at cryogenic temperature and the use of simplified transistor models such as s-EKV or ACM.
Project description: Industrially fabricated devices based on the fully-depleted silicon-on-insulator (FD-
SOI) technology have shown to be excellent candidates for cryogenic temperature operation. Building on our previous studies and most recent results, the goal of this PhD is to implement microelectronic functions in 28 nm FD-SOI technology for the control and readout of silicon quantum bits. LUT data extracted from available 4 K technology characterization will be used to optimize the design of new circuit functions operating with ultra-lower power consumption. A LUT-based design environment under development at TIMA Laboratory will be considered for this. The circuits functionality will be further validated using s-EKV transistor models working at 4 K available at CEA-LETI, before layout and fabrication in a standard STMicroelectronics process. The fabricated circuits will be measured at cryogenic temperatures at CEA-LETI. Circuits functions that are targeted for design and fabrication using the available design environments include RF LNA amplifiers, passive filters and analog signal generators working at a few GHz. The design and optimization of lower frequency transimpedance or charge amplifiers may also be considered.

Required skills : A candidate with an engineering background on RF microelectronics is required, with experience in the use of E-CAD frameworks such as Cadence Virtuoso and Keysight ADS. Good programming skills are also important for the manipulation of the design environments, including the use of MATLAB. Experience with 3D electromagnetic simulation with Ansys HFSS or Keysight Momentum is a plus.

The Phd is funded by Q-loop project of the Institut de Recheche Technologique Nanoelec

Contexte de travail

The TIMA Laboratory (UMR 5159) is a public research laboratory under the supervision of the CNRS (French National Centre for Scientific Research), Grenoble INP (Grenoble Institute of Technology), and UGA (Université Grenoble Alpes). TIMA is composed of several cosmopolitan research teams, bringing together researchers and interns from all over the world. A large part of the research is carried out within the framework of collaborative projects with industrial and academic partners, funded by regional, national, and European programs. The PhD will take place between the TIMA Laboratory (RMS team) and CEA-LETI in Grenoble, France.

Le poste se situe dans un secteur relevant de la protection du potentiel scientifique et technique (PPST), et nécessite donc, conformément à la réglementation, que votre arrivée soit autorisée par l'autorité compétente du MESR.