Missions

The goal of the position is to:
i) develop an FPGA test platform embedding MRAM memories from the market with the aim of validating a complete high level processor architecture
ii) participate to the development of a secured processor architecture in the framework of fault attacks
iii) develop an MRAM memory model based on last Magnetic Tunnel Junction generations.
The work environment is twofold, first FPGA-based for the first part and ASIC-based for the second part, both being at digital level. However, modeling a memory still requires to perform electrical simulations and characterizations. Thus, a multidisciplinary work is expected.

Activités

- digital design
- FPGA synthesis and simulation
- test platform design
- validation process

Compétences

The applicant must have a PhD degree in Microelectronics and/or Nanoelectronics, with skills in the fields of digital circuit design, and good knowledge of programming languages (Python, Matlab, etc.). Device level design skills would be appreciated.

Contexte de travail

The post doctoral contract will be funded by the ANR (French National Research Agency) in the framework of the « SCREAM » ANR project selected in 2024. The work will be done in collaboration between LIRMM (UMR 5506 Université de Montpellier / CNRS), SPINTEC (UMR 8191 CEA / CNRS / Université Grenoble-Alpes / Grenoble INP) and EMSE (Ecole des Mines de Saint Etienne).