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(M/F) Scholarship on Artificial Intelligence for a FPGA bitstream interpretation

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Français - Anglais

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General information

Reference : UMR7606-BRUMOA-001
Workplace : PARIS 05
Date of publication : Monday, July 20, 2020
Scientific Responsible name : Andrea PINNA
Type of Contract : PhD Student contract / Thesis offer
Contract Period : 36 months
Start date of the thesis : 1 October 2020
Proportion of work : Full time
Remuneration : 2 135,00 € gross monthly

Description of the thesis topic

The PhD thesis is part of the CNRS PRC program in collaboration with the University of Toronto (Canada). This implies periods of visit in Canada during the three years of the thesis.
The PhD thesis will take place within the SYEL team of the Paris 6 Computer Science Laboratory (LIP6) at Sorbonne-University in Paris and it will be co-supervised by Prof. Sebastien PILLEMENT, from the IETR laboratory in Nantes.

The expected result of this PhD is a proof of concept for the bitstream interpretation through machine learning and inferences models in order to translate an architecture hardware configuration of an algorithm to another one. In the short-middle term, the objectives to be achieved are:
- The bitstream interpretation : definition of a two-dimensional model of a bitstream representing the spatial distribution of the architecture reconfigurable by its elementary blocks and their configuration (bitstream parser);
- The exploration of a deep convolutional network model enriched by a hybrid output inference model. This network will have as input the two-dimensional model of the bitstream and as output the different logical functions (combinatory an sequential) and their connections.

Work Context

Today, convolutional neural networks (CNNs) have proven their capabilities in many vision problems [3] like for classification. The recent success of CNN is mainly due to the considerable development of many deep architectures like AlexNet [2], GoogleNet [4] ResNet [1] and VGG [5]. The pre-processing required by this type of network is much weaker or even nonexistent, compared to other classification algorithms, because the topology of these networks makes it possible to learn the features necessary for classification. The network is made up of two parts, the first one apply, several features extractors, called convolution kernels to the inputs, and this can be repeated in several layers. The second part perform a classification task thanks to one or more fully connected layers. In this second part different levels of inference can be used and different classification models can be mixed.
In the other hand, design of efficient embedded systems rely more and more often on the use of reconfigurable architecture (FPGA), that offers a very high level of flexibility. The main process of these architectures rely on the configuration of the chip to adapt itself to a specific application. This process, called the reconfiguration, can be done at run-time on modern circuits. This capability of dynamic reconfiguration offers a big room of optimization in a lot of domain like security, telecommunications, automotive where adaptivity is of highest interest. However, this capability of adaptation is not well used as generating the different architecture configurations (the bitstreams) is a very complex task, requiring specialists and long processes.
In this work we propose to use CNN algorithms to carry out the hardware architecture configurations of modern dynamically reconfigurable FPGA. The main idea is to rely on already generated bitstreams implementing some functions, and to enable the FPGA to modify itself is configuration thanks to its embedded reconfiguration AI engine. This engine should enable dynamic optimizations and adaptations of the application depending on the execution context of the system.

Constraints and risks

To do this, the first step to perform is to define an open FPGA architecture. This step is required as commercial FPGA manufacturer (Intel or Xilinx) encrypt their bitstreams and do not provide any information on it. In order to have a proof of feasibility on a single platform, it will be necessary to define a virtual reconfigurable architecture closest to the current architectures with a granularity and a complexity of low-medium level (Virtex 7, or Virtex- from Xilinx) using the VTR framework [6] defined in Toronto University which is a partner of this project.
Based on this open architecture the study will then study the ability of a CNN to recognize, classify, from a bitstream, the underlying hardware architecture. The bitstream can be considered as a two-dimensional image composed of binary pixels (see Figure 1). These pixels are the configuration inputs for each block of the FPGA (SB: switch block, CB: connection block, CLB: configurable logic block). An important work to be done is to extract this type of information from a bitstream. Once the two-dimensional spatial representation of the bitstream is obtained (this is just a suggestion on how to interpret the bitstream), the second stage of the project will be the study and application of deep network models to this image to learn how to recognize the functions implemented.Finally based on the intermediate representation of the function implemented the adaptation process for optimization will be added to the embedded AI engine.
As a use case for the validation of these goals, we will focus on two simple examples: a finite impulse response (FIR) filtering function and a finite state machine (FSM). These two simple examples have the advantage of combining combinatorial and sequential aspects and can be optimized by slights modification of the architecture.

Additional Information

Required profile :
- Master in computer science or electronics ;
- The candidate must have solid skills in at least one of the following domains: FPGA architectures, model of hardware architecture systems, CNN algorithms and machine learning;
- Mastery or prior experience in the following fields will be highly appreciated: bitstream generation and VTR tools, knowledge interpretation and fusion symbolic models, binary and fuzzy threes.
Written communication skills (in French and/or English) is a prerequisite as well.
Applying candidates will prove and/or justify the requested knowledge and skills by providing:
A CV;
A motivation letter consistent with the proposed PhD project;
All documents attesting the requested skills and knowledge;
Academic records and marks of the two years of Master, or of the two last years of Engineer
school.

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