Description du sujet de thèse

Various solutions are under study for post-quantum cryptography. Among these solutions, isogenies between elliptic curves offer small key sizes but require more computation time than other solutions. The residue number representation (RNS) allows to parallelize some computations by splitting the operands into
small independent numbers. Representations derived from RNS have been studied to optimize certain cryptographic computations (e.g. ECC and homomorphic encryption). In addition, RNS offers possibilities to randomize some computations and to detect faults which can be interesting to protect circuits from some
physical attacks by observation or perturbation.

The thesis will focus on the study, implementation, validation and evaluation of hardware accelerators for post-quantum cryptography based on isogenies between elliptic curves. We will start by studying the state of the art of algorithms as well as their software and hardware implementations. In parallel to the study of the state of the art, the recruited person will complete his/her training. We will identify and select algorithms that can be implemented in FPGA. For each algorithm, we will study its theoretical aspects, we will perform
high level simulations, we will implement it on FPGA with different arithmetic optimizations and RNS representations, we will perform intensive functional validations and comparisons in simulation and on FPGA board. A possible second phase of the thesis will focus on the protection against physical attacks
by observation or perturbation. We will study the state of the art of such attacks and the proposed protections. Then we will implement on FPGAs known and/or new protections, in particular by studying the possibilities offered by RNS to randomize computations and detect faults. Finally we will evaluate the
implemented protections.

Profile for candidates:

This multidisciplinary thesis requires very good knowledge in several of the
following fields:
- asymmetric cryptography (ECC, RSA, euclidean networks, isogenies)
- design of FPGA architectures in Verilog or VHDL
- finite field arithmetic
- Python and C programming
- writing, synthesis and analysis of documents
- oral presentation and collaborative work

Typical candidates profiles:

- Master's degree or engineering degree in cryptography with very good knowledge of C and Python programming. The person recruited will be trained in FPGA design aspects. This profile being particularly rare in the industry and the government services, this thesis will provide very good
opportunities for the person recruited.
- Master's degree or engineering degree in embedded computing or digital electronics with very good knowledge in arithmetic and at least a good basis in cryptography. The person recruited will be trained in in the implementation aspects of cryptosystems.

Contexte de travail

The recruited person will be employed at the CNRS on a 3-year fixed-term contract (CDD) in the laboratory Lab-STICC UMR6285 (https://labsticc.fr/) on the site of ENSTA Bretagne (https://www.ensta-bretagne.fr/) in Brest and will be enrolled in a thesis in the SPIN Doctoral School (https://ed-spin.doctorat-
bretagne.fr/).

The thesis will take place in the PQ-TLS project (https://pepr-pq-tls.cnrs.fr) of the PEPR Quantum which gathers the French teams in this field.

Le poste se situe dans un secteur relevant de la protection du potentiel scientifique et technique (PPST), et nécessite donc, conformément à la réglementation, que votre arrivée soit autorisée par l'autorité compétente du MESR.

Contraintes et risques

The position is located in a domain that falls under the protection of the scientific and technical potential (PPST), and therefore requires, in accordance with the regulations, that the recruitment be authorized by the competent authority of the MESR.