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m/f PhD Physical design methods for exploring large scale superconducting quantum circuits

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Français - Anglais

Date Limite Candidature : lundi 28 juin 2021

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General information

Reference : UMR5506-AIDTOD-014
Date of publication : Monday, June 7, 2021
Scientific Responsible name : Aida TODRI-SANIAL
Type of Contract : PhD Student contract / Thesis offer
Contract Period : 36 months
Start date of the thesis : 1 October 2021
Proportion of work : Full time
Remuneration : 2 135,00 € gross monthly

Description of the thesis topic

Scaling the quantum processors from 100 to 1000 is a major challenge. Some recent developments for future quantum systems are on advanced packaging technologies, novel qubit coupling architectures, and quantum error correction. Qubits are important, but they must be high-quality qubits. However, scaling up qubits to huge numbers depends on many factors, including the quantum computer's technology, architecture, physics and the ability to fine-tune and engineer hardware components. Efforts will be required to address the emerging problems in efficiently manipulating large number of qubits with exceptionally high fidelity. Also, adapting large-scale device to quantum error correction code is needed to realize a fault-tolerant quantum computer. There are many lessons to be learned from CAD EDA community and across other fields of machine learning. Error-correcting research will be more and more important as we scale toward large scale quantum processors. There is a need to investigate both hardware design and software for solutions to handle errors at a level necessary for million-qubit machines.

Work Context

The two main objectives of this thesis are on the development of physical design methods to investigate the scalability challenges to thousands of qubits while taking into account quantum architecture, qubit coupling topology, calibration data and crosstalk. Second objective is on the development of error mitigation design methods for large scale circuits while taking inspiration for design and fault tolerant methods from classical computing.

Constraints and risks


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