Description du sujet de thèse

Semiconductor technologies for computing hardware are poised to pursue performance scaling through disaggregation (chiplets) of accelerator-rich architectures employing advanced paradigms such as approximate, vector and stochastic computing, as well as diversified integration of non-volatile memory, advanced 3D transistors, photonic and RF interconnect. The dimensionality of design space for computing hardware, from data centers to edge computing devices, is growing exponentially at a time when technology orientation is critical.
To explore this vast design space, co-optimization techniques covering technology, circuits and systems and integrating the entire design value chain from technology models to application benchmarking are necessary. Such approaches require circuit and architecture design/synthesis and simulation tools, manufacturing process data, software aspects, compilers. The main objective of this work will be to enable the projection of technological developments of single emerging nanodevices on the design and performance of complex circuits and architectures for advanced applications. The work will initially be focused on the design and use of emerging non-volatile memory circuits in in-memory computing architectures for tensor processing and artificial intelligence hardware.
In the framework of a large-scale national research project (PEPR Electronique – CHOOSE) and in collaboration with CEA Grenoble and other research partners, the Electronics group at INL aims to research novel design-technology co-optimization techniques to explore energy-efficient machine learning accelerators based on advanced and emerging technologies for edge computing. In this context we are currently looking for a (m/f) PhD student for a 3-year contract.
Job description
This thesis aims to set up an open methodology allowing design-technology co-optimization, to make the link between emerging technologies and hardware operators. Based on a pre-existing tool developed at INL, the work will involve (i) formalizing technology parameter sets and development roadmaps, as well as agile calibration techniques of compact models, (ii) fast circuit simulation techniques and performance metric extraction, (iii) fast optimization techniques and Pareto front extraction and modeling. Put together, this work will enable the versatile creation of circuit design space models based on emerging technologies, in view of scaling up and coupling to system-technology co-optimization.
The work will involve circuit, behavioral and system-level modeling of advanced CMOS and NVM-enhanced logic and memory circuits, multi-objective optimization methodologies and benchmarking.
As a member of a team set up to work on this topic with the support of several sources of funding at national and European level, you will also be expected to supervise MSc students.
Profile
You have or are about to obtain an MSc in Electronic Engineering / Computer Science and have studied closely at least one of the following areas: analog / digital integrated circuit design, multi-disciplinary or system-level modelling. Knowledge of Cadence, Verilog, SystemC is a plus. Fluency in French is also a plus but is not mandatory.

Contexte de travail

INL is a 200-strong research institute based in Lyon, France, carrying out fundamental and applied research in electronics, semiconductor materials, photonics and biotechnologies. The Heterogeneous Systems Design group is a leader in the area of advanced nanoelectronic design, with research projects and collaborations at both national and European level. Recent highlights include the development of high-performance design strategies for complex 3D integrated circuits, ferroelectric logic in memory, VNWFET-based logic and silicon photonic computing.

Le poste se situe dans un secteur relevant de la protection du potentiel scientifique et technique (PPST), et nécessite donc, conformément à la réglementation, que votre arrivée soit autorisée par l'autorité compétente du MESR.