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Reference : UMR8191-GREDIP-002
Workplace : GRENOBLE
Date of publication : Thursday, November 07, 2019
Type of Contract : FTC Technical / Administrative
Contract Period : 24 months
Expected date of employment : 1 June 2020
Proportion of work : Full time
Remuneration : 2650€ - 3050€
Desired level of education : PhD
Experience required : Indifferent
Micro and nano electronics integrated circuit domain is today mainly driven by the advent of the internet of things for which the constraints are strong, especially in terms of power consumption and autonomy, not only during the computing phases, but also during the standby or sleep phases. In such application, the circuit behavior also has to meet new constraints mainly linked to changing energetic environment, automatic wake up on event, data storage when the circuit is sporadically turned off, and ultra-low voltage power supply for instance. The insertion of non-volatility is a crucial element to reach such objectives. Today efforts mainly focus on out-of-plane Spin Transfer Torque switching Magnetic Tunnel Junctions (STT-MTJ), that are dense using 2 terminals. A new generation seems to be much more promising for the coming years, according to the state of the art. These are Spin Orbit Torque MRAM (SOT-MRAM), for which SPINTEC has a great knowledge and experience. In contrast to that STT-MTJ, this SOT-MRAM has the main advantage to have 3 terminals. This enables to separate writing and reading paths, leading to an improved robustness and endurance. One of the objective of the project is the implementation of this hybrid solution on a 28nm FDSOI technology, which is today one of the emerging solutions energetically efficient, particularly with the use of its body biasing capabilities.
- The main tasks of this position would be to design and implement a non-volatile low-power microprocessor on an ASIC platform, on a very advanced process such as 28nm FD-SOI.
- The processor code will be provided by partners or open source. However, strategic modifications of the architecture and/or the implementation will be considered to take advantage of the non-volatility and the FDSOI technology. The non-volatility will be based on both STT-MTJ and SOT-MTJ standard cells developed within the project, in the framework of this NV-APROC project.
- The candidate can be either a 1-4 year experienced digital engineer or a post-doctorante applicant.
- The candidate will have first to modify source codes of the microprocessor to meet the relevant architecture that will be defined during the next months.
- Then the candidate will develop, with the help of the IC Design group, a specific digital design flow that enables to run simulations, synthesis and place and route jobs using these specific cells.
- Then, this processor will be simulated, synthetized, and placed & routed in order to be as much efficient as possible, targeting the milestones and project requirements such as low-power capabilities.
- A solid knowledge of processor architecture and digital design techniques, synthesis and Place and Route is mandatory for this position.
- Since the global target is a low-power ASIC, knowledge in clock and/or power gating and any other low-power techniques would be also appreciated.
- Knowledge on MRAM would be an advantage but not mandatory.
The candidate will be integrated to the CEA/CNRS/UGA - SPINTEC's Spintronics IC Design team in Grenoble, giving support on spintronics and CMOS/Magnetic ideas and strategies, in close collaboration with LIRMM laboratory and CEA-LETI/DACLE design team.
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