Missions

Although TEEs provide a layer of security to an embedded system, some work has shown that they can still leak information. RISC-V-based TEEs, such as Keystone and Penglai, have their definitions mainly based on PMP configurations. We want to investigate how the processor itself can be upgraded with hardware mechanisms to improve the security of the TEE against non-physical microarchitectural side-channel attacks such as electromagnetic or laser attacks. As part of this post-doctoral position, we would like to investigate how we can propose hardware extensions to provide additional services to RISC-V TEEs that would go beyond the solutions described in existing studies.

Given the nature of the work to be carried out, the person recruited may be required to collaborate with other researchers at the host site.

Activities

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- Studying which TEEs for RISC-V can be enhanced with hardware protection mechanisms.
- Studying the implementation of the previously identified mechanisms in a RISC-V processor such as those proposed by the OpenHwGroup (CV32E40P or CVA6).
- Evaluating the security and performance of the implemented mechanisms.

Skills

- Knowledge of one or more hardware description languages.

- Experience of low-level C language. Knowledge of assembler is a plus.

- Knowledge of processor architecture.

Work Context

Position open for an initial period of 12 months. Depending on results, the position may be extended for up to a further 12 months.

The postdoctoral fellow will work within the ARCAD team of the Lab-STICC laboratory. The supervising team is located at ENSTA in Brest.

The position is located in a sector under the protection of scientific and technical potential (PPST), and therefore requires, in accordance with the regulations, that your arrival is authorized by the competent authority of the MESR.

Constraints and risks

No risks associated with the position described in this offer.