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Portail > Offres > Offre UMR5506-AIDTOD-015 - h/f Ingénieur de Recherche - Modélisation et simulation d'un réseau de distribution d'alimentation backside pour les nœuds sub-nanometrique

m/f Research Engineer - Backside Power Delivery Network Modeling and Simulation

This offer is available in the following languages:
Français - Anglais

Date Limite Candidature : vendredi 30 juillet 2021

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General information

Reference : UMR5506-AIDTOD-015
Workplace : MONTPELLIER
Date of publication : Friday, June 18, 2021
Type of Contract : FTC Technical / Administrative
Contract Period : 12 months
Expected date of employment : 1 September 2021
Proportion of work : Full time
Remuneration : between 2,400 et 2600 euro gross monthly
Desired level of education : Engineer
Experience required : Indifferent

Missions

The design of power delivery in high-performance digital systems such as CPUs, GPU, etc., is becoming an increasingly difficult task. Power delivery network (PDN) should be designed for minimal power supply noise (PSN) while not occupying a significant portion of the area. Power supply noise can negatively impact system performance by introducing clock jitter, voltage droop, and even reduced reliability. Hence, PDN design and analysis take a central role in chip design.

With scaling to sub-nanometer nodes (nanosheet devices), a novel PDN configuration is implemented – a backside PDN configuration which separates PDN from the rest of the back-end-of-line interconnects. A backside PDN is achieved by using through silicon via (TSVs), and power and ground metal lines are implemented on the backside of the die to improve power integrity and core area utilization.

Vertically stacked nanosheet devices are considered the next generation of transistors, which can make more efficient use of device height and size. Another key scaling factor is the integrated power rail (BPR). These BPRS are integrated into the FEOL of the chip rather than the BEOL, which will free up interconnect resources for routing.

Further nanosheet scaling below 5nm will be limited by the routing space. This approach requires a complete re-design of the existing architectures for both backside PDN design and BEOL interconnects. Furthermore, to reduce the resistivity of the power metal lines, alternative filling metal to Copper (Cu) are being explored, such as Ruthenium (Ru). This work aims to explore the benefits and costs of a backside power delivery network for different benchmarks in terms of power supply noise, performance, reliability, thermal integrity, and power consumption. Physical design methods will be developed to optimize the distribution of power delivery for exploring the scalability of the backside PDN.

Activities

Further nanosheet scaling below 5nm will be limited by the routing space. This approach requires a complete re-design of the existing architectures for both backside PDN design and BEOL interconnects. Furthermore, to reduce the resistivity of the power metal lines, alternative filling metal to Copper (Cu) are being explored, such as Ruthenium (Ru). This work aims to explore the benefits and costs of a backside power delivery network for different benchmarks in terms of power supply noise, performance, reliability, thermal integrity, and power consumption. Physical design methods will be developed to optimize the distribution of power delivery for exploring the scalability of the backside PDN.

This work will be performed in the BPIFrance IT-2nm-FR project framework with collaboration with industrial and academic partners involved in sub-nanometer technology scaling and will provide scientific and technical support throughout this research.

Skills

We are looking for an excellent and highly motivated candidate to join our team at the Microelectronics Department, LIRMM, Montpellier, France. English fluency for both written and oral communication is a must. French is not mandatory, and candidates can follow French courses if wanted.

The following skills and qualifications are required:
- degree in electrical engineering or computer engineering with emphasis on VLSI design
- prior experience on transistor/circuit/system-level design (schematic, layout), simulation, analysis, placement & routing, EDA CAD tools
- prior experience with circuit timing and electrical analysis
- prior experience with programming languages, i.e., python, Matlab, C++, VHDL, Verilog, HSPICE, etc.

Work Context

This work will be conducted at LIRMM, Montpellier, France.

Constraints and risks

n/a

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